1. Field of the Invention
The present invention relates to a semiconductor device production method and a semiconductor device.
2. Description of Related Art
A DTI (deep trench isolation) technique is known as a device isolation technique for electrically isolating a high breakdown voltage element such as a high breakdown voltage MOSFET (metal oxide semiconductor field effect transistor) from other element.
FIG. 9 is a schematic sectional view showing the construction of a semiconductor device employing the DTI technique.
The semiconductor device 101 includes a thick SOI (silicon-on-insulator) substrate 102. The thick SOI substrate 102 is configured such that an N-type epitaxial layer 105 of Si (silicon) is provided on a silicon substrate 103 via a BOX (buried oxide) layer 104 of SiO2 (silicon oxide).
An annular deep trench 106 is provided in the epitaxial layer 105 as extending thicknesswise through the epitaxial layer 105. Oxide films 107 of SiO2 are provided on side surfaces of the deep trench 106. The deep trench 106 is filled with polysilicon 108 with the intervention of the oxide films 107. A region surrounded by the deep trench 106 serves as an element formation region 109 which is isolated from its peripheral region.
A LOCOS oxide film 110 is selectively provided in a surface portion of the epitaxial layer 105 in the element formation region 109. A high breakdown voltage element (e.g., MOSFET) 111 and a floating capacitor 112 are provided in the element formation region 109. Further, the thick SOI substrate 102 is covered with an interlayer dielectric film 113 of SiO2.
For production of the semiconductor device 101, the deep trench 106 is first formed in the epitaxial layer 105, and then filled with the polysilicon 108 with the intervention of the oxide films 107. Thus, the element formation region 109 is isolated from its peripheral region. Thereafter, the LOCOS oxide film 110 is formed in the surface portion of the epitaxial layer 105 in the element formation region 109 by a LOCOS (local-oxidation-of-silicon) method. Then, an impurity is selectively implanted into the surface portion of the epitaxial layer 105 in the element formation region 109 by an ion implantation method, whereby impurity regions including a source region and a drain region of the P-channel MOSFET 111 are formed.
In the formation of the LOCOS oxide film 110, a heat treatment is performed. Further, a heat treatment is performed for activation of the impurity implanted into the epitaxial layer 105 in the formation of the impurity regions. When the heat treatments are performed, stress occurring due to a difference in material between the epitaxial layer 105 and the oxide films 107 is concentrated on portions of the epitaxial layer 105 adjacent to upper and lower edges of the trench 106. Therefore, the repetitive heat treatments may result in crystal defects 114 occurring in the portions of the epitaxial layer 105 adjacent to the upper and lower edges of the trench 106 due to the concentration of the stress.